1. Field of the Invention
This invention relates to processor memory read accesses and, more particularly, to handling excess read data.
2. Description of the Related Art
Since s computer system's main memory is typically designed for density rather than speed, microprocessor designers have added caches to their designs to reduce the microprocessor's need to directly access main memory. A cache is a small memory that is more quickly accessible than the main memory. Caches are typically constructed of fast memory cells such as static random access memories (SRAMs) which have faster access times and bandwidth than the memories used for the main system memory (typically dynamic random access memories (DRAMs) or synchronous dynamic random access memories (SDRAMs)).
Modern microprocessors typically include on-chip cache memory. In many cases, microprocessors include an on-chip hierarchical cache structure that may include a level one (L1), a level two (L2) and in some cases a level three (L3) cache memory. Typical cache hierarchies may employ a small fast L1, cache that may be used to store the most frequently used cache lines. The L2 may be a larger and possibly slower cache for storing cache lines that are accessed but don't fit in the L1. The L3 cache may be still larger than the L2 cache and may be used to store cache lines that are accessed but do not fit in the L2 cache. Having a cache hierarchy as described above may improve processor performance by reducing the latencies associated with memory access by the processor core.
As successive generations of DRAM that is used for main system memory have evolved, the data burst transfer sizes have increased. Generally speaking, the burst transfer size refers to the size at which the DRAM can most efficiently transfer data resulting in the highest bandwidth. These newer DRAMs may transfer data in units that are greater than the size (cache line) that many processor cores can handle efficiently.